Design and Implementation of 64 bit High Speed Floating Point Multiplier for DSP Applications

Authors

  • Pooja Krishnamurthy Revankar, Dr. H. C. Hadimani, Dr. Udara Yedukondalu

DOI:

https://doi.org/10.17762/msea.v71i3.216

Abstract

Floating point number’s multiplication is the most important process in the area of graph theory, multidimensional graphics, and digital signal processing, high performance computing etc.  However,  computers  use  binary  numbers  and  it  would  like  more  precision however, it was found that binary numbers should be precise enough for most scientific and engineering calculations. So it was decided to double the amount of memory allocated. The Binary Floating point numbers are represented in Single and Double formats. The Single consist of 32 bits and the Double consist of 64 bits. The formats are composed of 3 fields; Sign, Exponent and Mantissa. The performance of Mantissa calculation Unit dominates overall performance of the Floating Point Multiplier. Many researchers have investigated the design of multiplier with different approaches. In this paper, we present the overview of work done by various researchers in their literature towards the design of Floating Point Multiplier. The creation of floating point units under a collection of area, latency and throughput constraint is an important ant consideration for system designers.

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Published

2022-06-09

How to Cite

Pooja Krishnamurthy Revankar, Dr. H. C. Hadimani, Dr. Udara Yedukondalu. (2022). Design and Implementation of 64 bit High Speed Floating Point Multiplier for DSP Applications. Mathematical Statistician and Engineering Applications, 71(3), 767 –. https://doi.org/10.17762/msea.v71i3.216

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Articles