Increased Clock Gating Efficiency for SRAM and Sequential Circuits

Authors

  • Dr. D. R. V. A. Sharath Kumar, Sudhir Dakey

DOI:

https://doi.org/10.17762/msea.v71i3.270

Abstract

Many different kinds of VLSI architectures find utility in time-critical situations. This study explores several methods for reducing power consumption in VLSI circuits. Combining clock frequency control, switching activity, and scaling factor are just three examples of the many existing methods for conserving power. As glitching and clock triggering difficulties become more common, the suggested study implemented a better clock gating circuit. This work proposes a method for decreasing power consumption through the use of clock gating based on a D-latch model. To reduce clock switching issues like gitching and clocking, a buffer circuit placed between the source and load circuits and integrated clock triggering on the LATCH circuit could be implemented. The SRAM and sequential counter circuits in this implementation are optimized for performance while adhering to the power-decrease method. Many practical uses rely heavily on specialized circuits designed for them, such as FPGAs and DSPs. Power reduction results from SRAM and sequential circuits need to be evaluated through experimental study. As compared to earlier studies, improvements in coverage, power, and latency were achieved. The majority of the design is done in Xilinx 14.2 ISE.

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Published

2022-06-09

How to Cite

Dr. D. R. V. A. Sharath Kumar, Sudhir Dakey. (2022). Increased Clock Gating Efficiency for SRAM and Sequential Circuits. Mathematical Statistician and Engineering Applications, 71(3), 1029 –. https://doi.org/10.17762/msea.v71i3.270

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Articles